Semiconductor memory device having cell array divided into a plurality of cell blocks

ABSTRACT

A semiconductor memory device includes a cell array having a plurality of memory cells grouped into a plurality of cell blocks and arranged in a matrix form, a plurality of word lines, a plurality of bit lines, bit line sense amplifiers (S/A), a cell block selection circuit, a plurality of data I/O lines, row decoders, a plurality of column selection signal lines, column decoders and a data buffer circuit. The data buffer circuit includes a first precharge circuit, connected to the data I/O lines, for precharging the data I/O lines to the same potential as a precharge potential of the bit lines, a second precharge circuit, connected to the data I/O lines, for precharging the data I/O lines to a potential different from the precharge potential of the bit lines, and selective drive circuit for generating control signals to be supplied to the first and second precharge circuit, and selectively driving the first and second precharge circuits to sense the data read out to the data I/O lines on the basis of the control signals.

This application is a continuation of application Ser. No. 07/608,732,filed on Nov. 5, 1990, now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device such as ahigh integrated DRAM having a cell array divided into a plurality ofcell blocks, wherein cell block selection is performed.

2. Description of the Related Art

In order to form a highly integrated DRAM, micro-patterning of elementsand lines must be realized, and a cell array and a cell array drivecircuit must be efficiently laid out within a predetermined chip area.In addition, the reading rate of cell data must be increased bydecreasing a ratio C_(B) /C_(S) of the capacity C_(S) of a memory cellto a capacity C_(B) of bit lines. Furthermore, in order to reduce thepower consumption due to charge/discharge of bit lines, the cell arraymust be divided into a plurality of cell blocks in the bit linedirection. A highly integrated DRAM using a divided bit line and commonY-decoder method is inevitably required to satisfy these demands.

In order to realize this method, for example, a cell array is dividedinto four or eight cell blocks in the bit line direction. Bit lines inthe respective cell blocks are independent of each other. A data I/Oline shared by two cell blocks is arranged between two adjacent cellblocks. The bit lines in a selected one of the two adjacent cell blocksare connected to a data I/O line through a block selection gate and acolumn selection gate. A column selection signal line for controlling acolumn selection gate is continuously formed by a metal wire on the cellarray constituted by the plurality of divided cell blocks, and a columnselection signal as an output from a Y-decoder (i.e., column decoder) issupplied to the column selection signal line. A method of sharing atleast part of a sense amplifier for bit line between adjacent cellblocks, i.e., a common sense amplifier method, is normally employed.

In a bit line precharge system of such a DRAM, it is known that aneffective measure to reduce the power consumption and increase the speedof a bit line sense operation is to precharge bit lines at (1/2)Vcc.

A data I/O line, however, is preferably precharged to Vcc for thefollowing reasons. First, assuming that the I/O line is precharged tothe same potential as that of the bit lines, i.e., (1/2)Vcc, when amemory cell of a selected cell block is re-stored, an electric potentialon bit line tends to be pulled up to an I/O line potential. A bit linesense amplifier is normally constituted by an NMOS sense amplifier and aPMOS sense amplifier. The NMOS sense amplifier is used to amplify asmall signal. The PMOS sense amplifier is used to raise the potential ofan "H"-level bit line to Vcc. For this reason, the drive power of thePMOS sense amplifier is not originally set to be large. Therefore, whena bit line is electrically connected to an I/O line potential, since theelectric potential on bit line is pulled up to the I/O line, the PMOSsense amplifier cannot satisfactorily raise the "H"-level bit linepotential to Vcc. This phenomenon becomes conspicuous especially when anI/O line has a large capacity, and abnormal operations may be caused.Second, if an I/O line can be precharged to Vcc, the initial sensingtime of the I/O line of circuit of a bit line sense amplifier can beshortened.

The conventional DRAM of the divided bit line and common Y-decodermethod, however, does not employ the precharge method, in which bitlines are precharged to (1/2)Vcc and an I/O lines are precharged to Vcc,for the following reason. Each column selection signal line iscontinuously arranged across a plurality of cell blocks and is connectedto the column selection gates of the respective cell blocks. With thisarrangement, when a given column selection signal is selected, thecolumn selection gates of non-selected cell blocks which data should benot read out are opened. Subsequently, bit line sense amplifiers locatedoutside the selection gates of the non-selected cell blocks andprecharged to (1/2)Vcc are connected to I/O lines precharged to Vcc. Asa result, the precharge potentials of the bit line sense amplifier issubjected to breakdown. The precharge method has not been employed forthe above-described reason.

As described above, in the conventional DRAM of the divided bit line andcommon Y-decoder method, the precharge potential of each bit line cannotbe set to be (1/2)Vcc and the precharge potential of each I/O linecannot be set to be Vcc. This interferes with realization of a furtherreduction in power consumption and an increase in operation speed.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a DRAM of a dividedbit line and common Y-decoder method, which can employ a prechargemethod in which each bit line is precharged to (1/2)Vcc and each I/Oline is precharged to Vcc, so as to realize an increase in operationspeed and a reduction in power consumption.

The characteristic feature is that DRAM formed in accordance with thepresent invention comprises:

a cell array including

a plurality of memory cells grouped into a plurality of cell blocks andarranged in a matrix form,

a plurality of word lines, arranged in each of the cell blocks in acolumn direction, for driving the memory cells in the column direction,

a plurality of bit lines, arranged to cross the word lines, fortransferring data to/from the selected memory cells, and

bit line sense amplifiers respectively connected to the bit lines;

a cell block selection circuit for selecting one of the plurality ofcell blocks of the cell array on active cycle;

a plurality of data I/O lines to which the bit lines in the cell blockselected by the cell block selection circuit are connected throughcolumn selection gates;

row decoders for selectively driving the word lines;

a plurality of column selection signal lines arranged across theplurality of cell blocks of the cell array and connected to the columnselection gates of the cell blocks;

column decoders for transferring column selection signals to the columnselection signal lines; and

a data buffer circuit, connected to the respective data I/O lines, forsensing data read out to the respective data I/O lines, the data buffercircuit including

a first precharge circuit, connected to the data I/O lines, forprecharging the data I/O lines at the same potential as a prechargepotential of the bit lines,

a second precharge circuit, connected to the data I/O lines, forprecharging the data I/O lines at a potential different from theprecharge potential of the bit lines, and

a selective drive circuit for selecting one of the first and secondprecharge circuits and driving the selected circuit.

In addition, a DRAM of the present invention comprises:

a cell array including

a plurality of memory cells grouped into a plurality of cell blocks andarranged in a matrix form,

a plurality of word lines, arranged in each of the cell blocks in acolumn direction, for driving the memory cells in the column direction,

a plurality of bit lines, arranged to cross the word lines, fortransferring data to/from the selected memory cells, and

bit line sense amplifiers respectively connected to the bit lines;

a cell block selection circuit for selecting one of the plurality ofcell blocks of the cell array on active cycle;

a plurality of data I/O lines to which the bit lines in the cell blockselected by the cell block selection circuit are connected throughcolumn selection gates;

row decoders for selectively driving the word lines;

a plurality of column selection signal lines arranged across theplurality of cell blocks of the cell array and connected to the columnselection gates of the cell blocks;

column decoders for transferring column selection signals to the columnselection signal lines; and

a selection gate control circuit which is arranged between the columnselection signal lines and the selection gates and is controlled by acontrol signal from the cell block selection circuit to transfer thecolumn selection signal to the selected column selection gate.

According to the present invention, with regard to bit lines and dataI/O lines connected to each other on active cycle, the following twostates can be obtained: a state wherein the precharge potential of thebit lines is (1/2)Vcc, and a state wherein the precharge potential ofthe data I/O lines is Vcc.

According to the first aspect of the present invention, all the data I/Olines on precharge cycle and non-selected data I/O lines on active cycleare set at the same precharge potential as that of the bit lines, i.e.,(1/2)Vcc. In addition, only data I/O lines selected on active cycle areselectively precharged to Vcc.

According to the second aspect of the present invention, the prechargepotential of all the data I/O lines is set at Vcc, and only the columnselection blocks of a cell block selected on active cycle can be opened.With this operation, in the selected cell block, the data I/O linesprecharged to Vcc are connected to the bit lines precharge at (1/2)Vcc.

In either of the first and second aspects, therefore, a relationship inpotential between non-selected cell block areas is not broken. Inaddition, since the precharge potential of each bit line from which datais read out is set to be (1/2)Vcc and the precharge potential of a dataI/O line is connected thereto is set to be Vcc, a high-speed data readoperation can be performed.

As described above, according to the present invention, both the methodof precharging bit lines to (1/2)Vcc and the method of precharging dataI/O lines to Vcc can be used. Therefore, there is provided a highlyintegrated DRAM which can realize a reduction in power consumption andin chip size without decreasing the operation speed.

Additional objects and advantages of the invention will be set forth inthe description which follows, and in part will be obvious from thedescription, or may be learned by practice of the invention. The objectsand advantages of the invention may be realized and obtained by means ofthe instrumentalities and combinations particularly pointed out in theappended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute apart of the specification, illustrate presently preferred embodiments ofthe invention, and together with the general description given above andthe detailed description of the preferred embodiments given below, serveto explain the principles of the invention.

FIG. 1 is a schematic diagram showing a chip layout of a DRAM of adivided bit line and common Y-decoder method according to the firstembodiment of the present invention;

FIG. 2 is a circuit diagram showing a one-column portion of a typicalsubcell array in the first embodiment;

FIG. 3 is a circuit diagram showing one cell block of the subcell array;

FIG. 4 is a circuit diagram showing a data I/O buffer section connectedto data I/O lines;

FIG. 5 is a timing chart for explaining an operation of the DRAMaccording to the first embodiment;

FIG. 6 is a circuit diagram showing a one-column portion of a subcellarray of a DRAM according to the second embodiment of the presentinvention;

FIG. 7 is a circuit diagram showing a data I/O buffer section connectedto data I/O lines of the DRAM;

FIG. 8 is a timing chart for explaining an operation of the DRAM of thesecond embodiment; and

FIG. 9 is a circuit diagram showing a one-column portion of a subcellarray of a DRAM according to the third embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A DRAM according to the first embodiment of the present invention willbe described below with reference to FIGS. 1 to 5.

FIG. 1 shows a schematic chip layout of a DRAM of a divided bit line andcommon Y-decoder method, in which a cell array is divided into eightcell blocks. FIG. 2 shows an arrangement of a one-column portion ofadjacent four cell blocks in FIG. 1. FIG. 3 shows an arrangement of onecell block in FIG. 2.

As shown in FIG. 1, a cell array arranged on a DRAM chip 1 is dividedinto eight cell blocks CA₀ to CA₇ in a bit line direction. These cellblocks CA₀ to CA₇ are grouped into two areas, i.e., an area includingthe cell blocks CA₀ to CA₃, and an area including the cell blocks CA₄ toCA₇. Row decoders 4₁ and 4₂ for selectively driving word lines arerespectively arranged at end portions of the area the cell blocks CA₀ toCA₃ and of the area including the cell blocks CA₄ to CA₇. Columnselection signal lines CSL_(i0) (i=1, 2, . . . , n) are continuouslyarranged on the four cell blocks CA₀ to CA₃ on the left side. Columnselection signal lines CSL_(i1) (i=1, 2, . . . , n) are continuouslyarranged on the four cell blocks CA₀ to CA₃ on the left side. Columnselection signal lines CSL_(i1) (i=1, 2 . . . , n) are continuouslyarranged on the four cell blocks CA₄ to CA₇ on the right side. Columndecoders 5₁ and 5₂ for performing column selection are arranged at endportions of these column selection signal lines CSL_(i0) and CSL_(i1).More specifically, one column decoder 5₁ is shared by the four cellblocks CA₀ to CA₃ on the left side, whereas the other column decoder 5₂is shared by the four cell blocks CA₄ to CA₇ on the right side.

In this DRAM, a bit line sense amplifier S/A and a data I/O line arearranged between the cell blocks CA₀ and CA₁. The bit line senseamplifier S/A and the data I/O line are shared by these cell blocks.Similarly, bit lines and data I/O lines are respectively arrangedbetween the cell blocks CA₂ and CA₃, between the cell blocks CA₄ andCA₅, and between CA₆ and CA₇. The I/O lines on the left side areconnected to a data line 3₁ through I/O buffer sections 2₁₁ and 2₁₂,respectively. The I/O lines on the right side are connected to a dataline 3₂ through I/O buffer sections 2₂₁ and 2₂₂, respectively. Thesedata lines 3₁ and 3₂ are connected to an external terminal through aninput-output circuit 8.

A peripheral circuit 7 including an address buffer, an RAS controlcircuit, a CAS control circuit, and the like, and a cell block selectorcircuit 6 to be controlled by the peripheral circuit 7 are arrangedbetween the two column decoders 5₁ and 5₂. The cell block selectorcircuit 6 has a function of selecting one cell block on active cycle.

FIG. 2 shows a cell array in more detail. FIG. 2 shows a detailedarrangement of a one-column portion of a subcell array 10 constituted bythe four cell blocks CA₀ to CA₃ on the left side. FIG. 3 shows adetailed arrangement of the one cell block CA₀ in FIG. 2. In thisembodiment, a cell array has a folded bit line structure.

A description will be made below in consideration of the cell block CA₀.As shown in FIG. 3, a large number of memory cells MC₁, MC₂ . . . eachhaving a one-transistor/one-capacitor structure are respectivelyconnected to a pair of bit lines BL₀ and BL₀ . Dummy cells DC₁ and DC₂are respectively connected to the bit lines BL₀ and BL₀ . Word linesWL₁, WL₂, . . . for selectively driving the memory cells MC₁, MC₂, . . ., and dummy word lines DWL₁ and DWL₂ for selectively driving the dummycells DC₁ and DC₂ are arranged to cross the bit lines BL₀ and BL₀ .These word lines and dummy word lines are designed to simultaneouslydrive memory cells and dummy cells corresponding to other columns.

A description will be made below in consideration of the cell blocks CA₀and CA₁. Each bit line sense amplifier S/A comprises a PMOS senseamplifier PSA constituted by a PMOS flip-flop, and an NMOS senseamplifier NSA constituted by an NMOS flip-flop. Of these senseamplifiers, the PMOS sense amplifier PSA is arranged in each of the cellblocks CA₀ and CA₁. The NMOS sense amplifier NSA is arranged outside thecell blocks CA₀ and CA₁ so as to be shared by the two adjacent cellblocks CA₀ and CA₁. Block selection gates Q₅ and Q₆ to be controlled bya block selection signal BSL₁ are respectively arranged between theinternal bit lines BL₀ and BL₀ in the cell block CA₀, and betweenexternal bit lines BL₀₁ and BL₀₁ which the common NMOX sense amplifierNSA is arranged. Similarly, block selection gates Q₇ and Q₈ to becontrolled by a block selection signal BSL₀ are respectively connectedbetween the cell block CA₁ and the external bit lines BL₀₁ and BL₀₁.

A bit line equalization circuit EQ shared by the two cell blocks CA₀ andCA₁ is arranged between the bit lines BL₀₁ and BL₀₁ on the right side ofthe common NMOS sense amplifier NSA. The bit line equalization circuitEQ comprises an equalization MOS transistor Q₃₁ for short-circuiting thebit lines BL₀₁ and BL₀₁ as a pair, and precharge MOS transistors Q₃₂ andQ₃₃ for setting these bit lines BL₀₁ and BL₀₁ to a precharge potential(1/2)Vcc. The bit lines BL₀₁ and BL₀₁ having the common NMOS senseamplifier NSA arranged therebetween are respectively connected to dataI/O lines I/O and I/O through the column selection gates Q₁ and Q₂. Thecell blocks CA₂ and CA₃ adjacent to these cell blocks CA₀ and CA₁ havethe same arrangement as described above.

The column selection signal lines CSL_(i0) for transmitting columnselection signals from the column decoder are arranged across the areaof the four cell blocks CA₀ to CA₃. The column selection signalsCSL_(i0) are connected to the column selection gates Q₁, Q₂, Q₃, and Q₄of the four cell blocks CA₀ to CA₃ so as to simultaneously drive thesecolumn selection gates.

FIG. 4 shows a detailed arrangement of an I/O buffer section connectedto the above-described subcell array 10. With regard to the cell blocksCA₀ and CA₁, the I/O buffer section includes an I/O buffer 16₁₁ and anI/O buffer control circuit 14₁. The I/O buffer 16₁₁ having a senseamplifier 11₁ is connected to a pair of I/O lines I/O₀₁ and I/O₀₁commonly provided for the adjacent cell blocks CA₀ and CA₁. This I/Obuffer 16₁₁ includes a first I/O line precharge circuit 13₁ forprecharging the I/O lines I/O₀₁ and I/O₀₁ to the same potential (1/2)Vccas that of the bit lines, and a second I/O precharge circuit 12₁ forprecharging the I/O lines I/O₀₁ and I/O₀₁ to the potential Vcc higherthan (1/2)Vcc.

The first precharge circuit 131 comprises an equalization n-channel MOStransistor Q₁₅ for short-circuiting the I/O lines I/O₀₁ and I/O₀₁ , andprecharge n-channel MOS transistors Q₁₃ and Q₁₄ for setting the I/Olines I/O₀₁ and I/C₀₁ to (1/2)Vcc. The second precharge circuit 12₁comprises an equalization p-channel MOS transistor Q₁₈ and prechargep-channel MOS transistors Q₁₆ and Q₁₇.

The I/O buffer control circuit 14₁ selectively drives the I/O buffer16₁₁ by using a precharge control signal CEQ and a sense control signalQSE.

An I/O buffer 16₁₂ including an I/O sense amplifier 11₂ is connected toa pair of I/O lines I/O₂₃ and I/O₂₃ commonly provided for other two cellblocks CA₂ and CA₃ in the same manner as described above. The I/O buffer16₁₂ includes first and second I/O precharge circuits 13₂ and 12₂. AnI/O buffer control circuit 14₂ is provided for the I/O buffer 16₁₂.

The cell block selection signals BSL₀ and BSL₁ are input to the I/Obuffer control circuit 14₁ as control signals. Cell block selectionsignals BSL₂ and BSL₃ are input to the I/O buffer control circuit 14₂ ascontrol signals. With this arrangement, when the cell block CA₀ or CA₁is selected, i.e., the signal BSL₀ is BSL₁ is set at "L" level, acontrol signal IOS₀₁ is set at "L" level, and the I/O sense amplifier11₁ in the I/O buffer 16₁₁ is activated. At this time, in the I/O buffer16₁₁, the control signal IOS₀₁ sets the first I/O line precharge circuit13₁ for (1/2)Vcc precharge in an inactive state, and the control signalCEQ₀₁ sets the second I/O line precharge circuit 12₁ for Vcc prechargein an active state. At this time, since an "H"-level control signalIOS₂₃ is supplied to the I/O sense amplifier 11₂ in the other I/O buffer16₁₂, the I/O sense amplifier 11₂ is not activated. The control signalIOS₂₃ sets the first I/O line precharge circuit 13₂ for (1/2)Vccprecharge in an active state, and the control signal CEQ₂₃ sets thesecond I/O line precharge circuit 12₂ for Vcc precharge in an inactivestate. If the cell block CA₂ or CA₃ is selected, the above-describedrelationship is reversed. These I/O buffers are connected to theinput-output circuit 8 through read/write data lines 3.

An operation of the DRAM of the divided bit line and common-Y decodermethod having the above-described arrangement will be described withreference to a timing chart in FIG. 5, in which the cell block CA₀ ofthe eight cell blocks CA₀ to CA₇ is selected as indicated by a hatchedportion in FIG. 1, and the data I/O line I/O₀₁ and I/O₀₁ are activated.Note that FIG. 5 shows the operation waveforms of the respective signalswhen the subcell array 10 consisting of the four cell block CA₀ to CA₃is taken into consideration.

The block selection signals BSL₀ to BSL₃ are at "H" level (i.e., Vcc)before they are set on active cycle. Therefore, all the cell blockselection gates Q₅ to Q₁₂ are in an ON state. When a row address isdetermined, for example, one block selection signal BSL₀ is set at "L"level. As a result, the block selection gates Q₇ and Q₈ are set in anOFF state, the cell block CA₁ of the two cell blocks CA₀ and CA₁ sharingthe NMOS sense amplifier NSA is disconnected from the NMOS senseamplifier NSA. At the same time, the buffer control circuit 14₁ of theI/O buffer section 2₁₁ receives the "L"-level block selection signalBSL₀ and the "H"-level block selection signal BSL₁ . The I/O selectionIOS₀₁ is set at "L" level by an AND gate G₁, so that the first prechargecircuit 13₁ for (1/2)Vcc precharge in the I/O buffer 16₁₁ is notoperated. In addition, the precharge control signal CEQ of "L" level andthe I/O selection signal IOS₀₁ of "L" level are input to an OR gate G₂so as to set the precharge control signal CEQ₀₁ at "L" level. As aresult, the second precharge circuit 12₁ for Vcc precharge is activated.Furthermore, the potential of the sense signal QSE₀₁ is raised from(1/2)Vcc to Vcc by the I/O selection signal IOS₀₁ of "L" level and thesense control signal QSE of "L" level. Hence, the reference electricpotential of the I/O sense amplifier 11₁ is increased to Vcc. With thisoperation, the I/O lines I/O₀₁ and I/O₀₁ which have been precharged to(1/2)Vcc are precharged to Vcc.

Meanwhile, a word line selected by the row decoder 4₁ is activated sothat data of a memory cell arranged along the selected word line in thecell block CA₀ and of a dummy cell arranged along a selected dummy lineare read out to the bit lines BL₀ and BL₀ . These data are transferredto the external bit lines BL₀₁ and BL₀₁ through block selection gates Q₅and Q₆. The NMOS sense amplifier NSA is activated, and the PMOS senseamplifier PSA is then activated. Subsequently, the bit lines BL₀₁ andBL₀₁ are respectively set at Vcc and 0. The column selection signalCSL_(i0) selected by the column decoder 5₁ is set at "H" level. As aresult, the column selection gates Q₁ and Q₂ are set in an ON state. Thedata on the bit lines BL₀₁ and BL₀₁ are read out to the I/O lines I/O₀₁and I/O₀₁ through these column selection gates Q₁ and Q₂. since theprecharge control signal CEQ is set at "H" level at the same time thatthe column selection signal CSL_(i0) is set at "H" level, the secondprecharge circuit 12₁ is set in an inactive state. Subsequently, thesense control signal QSE₀₁ is set at "L" level so that the I/O senseamplifier 11₁ is activated and the I/O lines I/O₀₁ and I/O₀₁ arerespectively set at Vcc and 0.

During this read operation, the block selection gates Q₇ and Q₈ of theother cell block CA₁ sharing the NMOS sense amplifier NSA with theselected cell block CA₀ is kept in an OFF state. That is, the cell blockCA₁ is disconnected from the NMOS sense amplifier NSA. Although theblock selection gates Q₉, Q₁₀, Q₁₁, and Q₁₂ of the other non-selectedcell blocks CA₂ and CA₃ are in an ON state, their precharge potentialstates are free from breakdown. More specifically, while the cell blockCA₀ is selected, both the block selection signals BSL₂ and BSL₃ are keptat "H" level, as shown in FIG. 5. Therefore, the control signal IOS₂₃ ofthe first precharge circuit 13₂ for (1/2)Vcc precharge is set at "H"level by the I/O buffer control circuit 14₂ of the I/O buffer section2₁₂ of the I/O lines I/O₂₃ and I/O₂₃ of the non-selected cell blocks CA₂and CA₃. Similarly, the control signal CEQ₂₃ of the second prechargecircuit 12₂ for Vcc precharge is kept at "H" level, and an activationsignal QSE₂₃ of the I/O sense amplifier 11₂ is kept at (1/2)Vcc. Thatis, the data I/O lines I/O₂₃ and I/O₂₃ are kept at (1/2)Vcc. Therefore,the column selection gates Q₃ and Q₄ are set in an ON state by the samecolumn selection signal CSL_(i0) . Since both the data I/O lines I/O₂₃and I/O₂₃ are set at a precharge potential of (1/2)Vcc, no problems areposed even if the NMOS sense amplifier of the non-selected cell blocksCA₂ and CA₃ is connected to the data I/O lines I/O₂₃ and I/O₂₃ .

When the active cycle is completed and a precharge cycle is set, the I/Olines precharged to Vcc on active cycle are precharged to (1/2)Vccagain.

In the first embodiment, the precharge method is employed in theabove-described manner, in which only I/O lines selected on active cycleare precharged to Vcc on the basis of the (1/2)Vcc precharge method.According to the DRAM of the first embodiment, therefore, both areduction in power consumption and in chip area by the (1/2)VCCprecharge method and an increase in operation speed by the Vcc prechargemethod can be realized. Vcc precharge of a selected I/O line may becompleted by the time that a column selection signal is activated.Therefore, a satisfactory margin can be set. That is, the method of thisembodiment does not interfere with an increase in operation speed anddoes not require an especially large MOS transistor for Vcc precharge.The selected I/O line is precharged to (1/2)Vcc again when the activecycle is completed and a precharge cycle is set. This operation,however, is performed at the same time that other bit lines and I/Olines are precharged, and hence no extra time is required.

A DRAM of a divided bit line and common-Y decoder method according tothe second embodiment of the present invention will be described belowwith reference to FIG. 6. The overall arrangement of the secondembodiment is the same as that of the first embodiment described withreference to FIG. 1. FIG. 6 shows an arrangement of a one-column portionof the DRAM in correspondence with the arrangement shown in FIG. 2. Thesame reference numerals in FIG. 6 denote the same parts as in FIG. 6,and a detailed description thereof will be omitted.

In the first embodiment, the column selection signal lines CSL_(i0)arranged across a plurality of cell blocks are directly connected to aplurality of column selection gates so as to simultaneously open/closethe column selection gates. In order to perform Vcc precharge of onlyselected I/O lines of a plurality of data I/O lines, Vcc precharge and(1/2)Vcc precharge circuits for selectively driving data I/O lines arearranged. In contrast to this, the second embodiment includes selectivedrive circuits 21a and 21b for selectively driving column selectiongates Q₁ and Q₂, and Q₃ and Q₄, as shown in FIG. 6. The selective drivecircuit 21a is arranged between column selection signal lines CSL_(i0)arranged across a plurality of cell blocks and the column selectiongates Q₁ and Q₂ to be driven thereby, whereas the selective drivecircuit 21b is arranged between the column selection signal linesCSL_(i0) and the column selection gates Q₃ and Q₄.

In the second embodiment, each of the selective drive circuits 21a and21b is constituted by a two-input NAND gate G₁₁ and a two-input AND gateG₁₂. The NAND gate of one selective drive circuit 21a receives two blockselection signals BSL₀ and BSL₁ . The NAND gate of the other selectivedrive circuit 21b receives remaining two block selection signals BSL₂and BSL₃ . One input terminal of each AND gate G₁₂ is connected to acorresponding column selection signal line CSL_(i0), and the other inputterminal is connected to the output of a corresponding one of the NANDgates G₁₁. An output from the AND gate G₁₂ of one selective drivecircuit 21a is used as a control signal for the column selection gatesQ₁ and Q₂ arranged between the cell blocks CA₀ and CA₁. An output fromthe AND gate G₁₂ of the other selective drive circuit 21b is used as acontrol signal for the column selection gates Q₃ and Q₄.

Two pairs of data I/O lines I/O₀₁ and I/O₀₁ , and I/O₂₃ and I/O₂₃ towhich the bit lines of this subcell array 10 are connected are connectedto an I/O line sense amplifier 22 and an I/O line precharge circuit 23for Vcc precharge, as shown in FIG. 7.

In the second embodiment having the above-described arrangement, whenone of the column selection signal lines CSL_(i0) is selected on activecycle, all the column selection gates Q₁ and Q₂, and Q₃ and Q₄ are notsimultaneously set in an ON state. A signal from the column selectionsignal line CSL_(i0) is selectively supplied to the column selectiongates Q₁ and Q₂ or Q₃ and Q₄ in accordance with selection of a cellblock.

An operation of the DRAM of this embodiment will be described in detailbelow with reference to FIG. 8. Similar to the description of the firstembodiment, FIG. 8 shows the operation waveforms of the respectivesignals appearing when data is read out from the cell block CA₀. All theblock selecting signals BSL₀ to BSL₃ are at "H" level before an activecycle is set. Therefore, all the cell block selection gates Q₅ to Q₁₂are in an ON state. When a row address is determined, for example, theblock selection signal BSL₀ is set at "L" level. As a result, the blockselection gates Q₇ and Q₈ are set in an OFF state. That is, the cellblock CA₁ of the two cell blocks CA₀ and CA₁ sharing the NMOS senseamplifier NSA is disconnected from the NMOS sense amplifier NSA.

A word line WL selected by a row decoder is activated, and data of aselected memory cell in the cell block CA₀ and of a dummy cell are readout to the bit lines BL₀ and BL₀ . These data are transferred toexternal bit lines BL₀₁ and BL₀₁ through the block selection gates Q₅and Q₆. The NMOS sense amplifier NSA is activated, and the PMOS senseamplifier PSA is then activated. As a result, the bit lines BL₀₁ andBL₀₁ are respectively set at Vcc and 0. Subsequently, the columnselection signal CSL_(i0) selected by a column decoder 5₁ is set at "H"level. Since the block selection signals BSL₀ and BSL₁ are respectivelyset at "H" level and "L" level at this time, an output control signalCSL_(ioa) from the selective drive circuit 21a is set at "H" level. As aresult, the column selection gates Q₁ and Q₂ are set in an ON state.Consequently, the data on the bit lines BL₀₁ and BL₀₁ are read out tothe I/O lines I/O₀₁ and I/O₀₁ through the column selection gates Q₁ andQ₂, respectively.

As described above, during this read operation, the block selectiongates Q₇ and Q₈ of the cell block CA₁, which share the NMOS senseamplifier NSA with the cell block CA₀, are kept in an OFF state. Thatis, the cell block CA₁ is disconnected from the NMOS sense amplifierNSA. On the other hand, the block selection gates Q₉, Q₁₀, Q₁₁, and Q₁₂of the other non-selected cell blocks CA₂ and CA₃ are in an ON state.However, the precharge potentials of these portions are free frombreakdown for the following reason. While the cell block CA₀ isselected, both the block selection signals BSL₂ and BSL₃ are kept at "H"level, as shown in FIG. 8. Thus, a control signal CSL_(iob) obtainedfrom the selective drive circuit 21b is kept at "L" level, and thecolumn selection gates Q₃ and Q₄ of the cell blocks CA₂ and CA₃ are keptin an OFF state. Therefore, the bit lines BL₂₃ and BL₂₃ precharged to(1/2)Vcc are not connected to the data I/O lines I/O₂₃ and I/O₂₃precharged to Vcc. As shown in FIG. 8, during this read operation, thebit lines BL₂₃ and BL₂₃ are kept at (1/2)Vcc, whereas the data I/O linesI/O₂₃ and I/O₂₃ are kept at Vcc.

As described above, in the second embodiment, (1/2)Vcc precharge of bitlines and Vcc precharge of I/O lines are simultaneously performed.

A DRAM according to the third embodiment of the present invention willbe described below with reference to FIG. 9. In the third embodiment,the selective drive circuits 21a and 21b in FIG. 6 are modified. Morespecifically, a circuit portion corresponding to the AND gate G₁₂ ineach of the selective drive circuits 21a and 21b is constituted by aninverter I, a transfer gate, and an n-channel MOS transistor Q43 forshort-circuit. The transfer gate consists of an n-channel MOS transistorQ41 and a p-channel MOS transistor Q42. Other arrangements are the sameas those in FIG. 6.

An operation of the third embodiment is the same as that of the secondembodiment. Similar to the second embodiment, assume that blockselection signals BSL₀ to BSL₃ are set in such a manner that the BSL₀="L" level and BSL₁ =BSL₂ =BSL₃ ="H" on active cycle. In this case, theoutput of a NAND gate G₁₁ of one selective drive circuit 21a is at "H"level. Therefore, both the MOS transistors Q₄₁ and Q₄₂ are in an ONstate, and the MOS transistor Q₄₃ is in an OFF state. A signal of "H"level from a column selection signal line CSL_(i0) is transferred tocolumn selection gates Q₁ and Q₂ through the selective drive circuit21a. The output of the NAND gate G₁₁ of the other selective drivecircuit 21b is set at "L" level. Consequently, the MOS transistors Q₄₁and Q₄₂ are in an OFF state, and the MOS transistor Q₄₃ is in an OFFstate. That is, the "H"-level signal from the column selection signalCSL_(i0) is not transferred to the column selection gates Q₃ and Q₄.

As described above, since column selection gates connected tonon-selected cell blocks are not rendered conductive, (1/2)Vcc prechargeof bit lines and Vcc precharge of data I/O lines can be simultaneouslyperformed.

In the third embodiment, the number of elements used for each of theselective drive circuits 21a and 21b is smaller than that in the secondembodiment described with reference to FIG. 6. More specifically, in thesecond embodiment, the AND gate G₁₂ is normally constituted by sixelements. In contrast to this, a portion corresponding to the AND gateG₁₂ in the third embodiment can be constituted by five elements, namelythe three MOS transistors Q₄₁ to Q₄₃, and two transistors constitutingthe inverter I. Since the selective drive circuits 21a and 21b must bearranged for each column selection signal line, even a decrease innumber of elements by one can greatly contribute a reduction in DRAMchip area.

The prevent invention is not limited to the above embodiments. Forexample, in the embodiments, a column decoder is located insubstantially the center of a DRAM chip. However, such an layout can bechanged as needed.

In addition, if NAND gates in selective drive circuits are arrangedoutside a cell array, the DRAM of the present invention can beintegrated at a high density. Furthermore, in the embodiments, a bitline precharge potential is set to be (1/2)Vcc, and a data I/O lineprecharge potential is set to be two or more values such as Vcc and(1/2)Vcc in the first embodiment and to be VCC only in the second andthird embodiments. However, proper precharge potentials other than thesevalues can be selected.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details, representative devices, andillustrated examples shown and described herein. Accordingly, variousmodifications may be made without departing from the spirit or scope ofthe general inventive concept as defined by the appended claims andtheir equivalents.

What is claimed is:
 1. A Dynamic Random Access Memory, comprising:a cellarray divided into a plurality of cell blocks, each cell blockincluding,a plurality of memory cells arranged in a matrix form, aplurality of word lines, arranged in a column direction, for selectingsaid memory cells in the column direction, a plurality of bit lines,arranged to cross said word lines, for transferring data to/from saidselected memory cell, and, bit line sense amplifiers respectivelyconnected to said bit lines; cell block selection means for selectingone of said plurality of cell blocks on active cycle; a plurality ofdata I/O lines to which said bit lines in a selected cell block selectedby said cell block selection means are connected through respectivecolumn selection gates; row decoder for selectively driving said wordlines in each cell block; a plurality of column selection signal linesarranged across said plurality of cell blocks, each column selectionsignal line commonly connected to associated column selection gates in asame column of said plurality of cell blocks; column decoder fortransferring column selection signals to said column selection signallines; and data buffer means, connected to said respective data I/Olines, for sensing data read out to said respective data I/O lines, saiddata buffer means including,first precharge means, connected to saiddata I/O lines, for precharging said data I/O lines at the same firstpotential as a precharge potential of said bit lines, second prechargemeans, connected to said data I/O lines, for precharging said data I/Olines at a second potential different from the precharge potential ofsaid bit lines, selective drive means for generating control signals tobe supplied to said first and second precharge means, and selectivelydriving said first and second precharge means to sense the data read outto said data I/O lines on the basis of the control signals, such thatsaid first precharge means precharges said data I/O lines connected tonon-selected cell blocks of said cell blocks to the first potential onactive cycle and on precharge cycle, and precharges a selected data I/Oline connected to said selected cell block to the first potential onprecharge cycle, and said second precharge means precharges saidselected data I/O line connected to said selected cell block to thesecond potential on active cycle, and I/O line sense amplifiers forsensing the data read out to said data I/O lines.
 2. A semiconductormemory device according to claim 1, wherein said first precharge meansprecharges said data I/O lines connected to non-selected cell blocks ofsaid cell blocks to (1/2)Vcc on active cycle and on precharge cycle, andprecharges said data I/O lines connected to said selected cell block to(1/2)Vcc on precharge cycle.
 3. A semiconductor memory device accordingto claim 2, wherein said first precharge means is arranged between apair of said data I/O lines and is connected to a (1/2)Vcc terminal. 4.A semiconductor memory device according to claim 1, wherein said secondprecharge means precharges said data I/O lines connected to saidselected cell block to Vcc on active cycle.
 5. A semiconductor memorydevice according to claim 4, wherein second precharge means is arrangedbetween a pair of said data I/O lines and is connected to a Vccterminal.
 6. A semiconductor memory device according to claim 1, whereinsaid precharge selective drive means is controlled by cell blockselection signals for selecting said adjacent cell blocks, and generatesthe control signals.
 7. A semiconductor memory device according to claim1, wherein said data buffer means is shared by said adjacent cellblocks.
 8. A semiconductor memory device according to claim 1, whereinat least some of said bit line sense amplifiers and said data I/O linesare shared by said adjacent cell blocks.
 9. A semiconductor memorydevice according to claim 1, wherein each of said bit line senseamplifiers is constituted by a PMOS sense amplifier arranged in each ofsaid cell blocks, and an NMOS sense amplifier arranged outside said cellblock selection gates of said cell blocks and shared by said twoadjacent cell blocks.
 10. A Dynamic Random Access Memory, comprising:acell array divided into a plurality of cell blocks, each cell blockincluding,a plurality of memory cells arranged in a matrix form, aplurality of word lines, arranged in a column direction, for selectingsaid memory cells in the column direction, a plurality of bit lines,arranged to cross said word lines, for transferring data to/from saidselected memory cells, said bit lines being precharged to a firstpotential, and, bit line sense amplifiers respectively connected to saidbit lines; cell block selection means for selecting one of saidplurality of cell blocks on active cycle; a plurality of data I/O linesto which said bit lines in a selected cell block selected by said cellblock selection means are connected through respective column selectiongates, a selected I/O line of said selected cell block having a secondpotential different from said first potential on an active cycle, andhaving said first potential on a precharge cycle, non-selected data I/Olines in non-selected cell blocks having the first potential on theactive cycle and the precharge cycle; row decoder for selectivelydriving said word lines in each cell block; a plurality of columnselection signal lines arranged across said plurality of cell blocks,each column selection signal line commonly coupled to associated columnselection gates in a same column of said plurality of cell blocks;column decoder for generating column selection signals to said columnselection signal lines; and selection gate control means, providedbetween said column selection signal lines and said column selectiongates, for receiving the associated column selection signal and gatingthe column selection gate of the selected cell block on the active cycleon the basis of the associated column selection signal, therebyprecharging said selected I/O line of said selected cell block to thesecond potential and maintaining said non-selected I/O lines ofnon-selected blocks to the first potential on the active cycle.
 11. Asemiconductor memory device according to claim 10, wherein saidselection gate control means is arranged between said column selectionsignal lines and said column selection gates and is controlled by a pairof control signals from said cell block selection means for selectingsaid adjacent cell blocks.
 12. A semiconductor memory device accordingto claim 11, wherein said selection gate control means is constituted byan NAND gate for receiving the respective cell block selection signalsfor said adjacent cell blocks, and an AND gate for receiving an outputfrom said NAND gate and the column selection signals.
 13. Asemiconductor memory device according to claim 12, wherein said AND gateis constituted by an inverter, a transfer gate consisting of ann-channel MOS transistor and a p-channel MOS transistor, and ann-channel MOS transistor for short circuit.
 14. A semiconductor memorydevice according to claim 10, wherein at least some of said bit linesense amplifiers and said data I/O lines are shared by said adjacentcell blocks.
 15. A semiconductor memory device according to claim 10,wherein each of said bit line sense amplifiers is constituted by a PMOSsense amplifier arranged in each of said cell blocks, and an NMOS senseamplifier arranged outside said cell block selection gates of said cellblocks and shared by said adjacent cell blocks.
 16. The Dynamic RandomAccess Memory according to claim 1, wherein the second potential ishigher than the first potential.
 17. The Dynamic Random Access Memoryaccording to claim 11, wherein the second potential is higher than thefirst potential.